1. Technical Field
The present invention is directed to an apparatus and method visualizing and analyzing resistance networks. More specifically, the present invention is directed to a mechanism for automatically generating a visual representation of a resistance network to facilitate visual verification and a mechanism for automatically generating equivalent point to point resistance.
2. Description of the Related Art
Resistance/capacitance (RC) parasitic extraction of cell and interconnect structures is an essential part of the integrated circuit design and verification process. The extracted RC parasitics are used for a number of different applications including delay, power drop, and electromigration analysis. Accurate resistance extraction is essential for these applications.
The extracted RC parasitics for individual nets in an integrated circuit can be very complex with hundreds or thousands of individual resistor and capacitor components. There are a number of tools, such as QuickCap available from Random Logic Corporation, that are used for the verification of accuracy of extracted capacitance.
Currently, the verification of the accuracy of the extracted resistance networks is very difficult and not generally done. If it is done at all, the analysis and verification of extracted resistance networks is performed manually. However, as more and more elements are integrated into smaller areas, the complexity of the corresponding extracted resistance networks makes it very difficult to manually verify the extracted results.
Thus, it would be beneficial to have an apparatus and method for automatically generating a visual representation of a resistance network that facilitates visual verification by a user. Moreover, it would be beneficial to have an apparatus and method for automatically generating equivalent point to point resistance for use in verifying the extracted resistances.